1. Field of the Invention
The present invention relates to electronic analog-to-digital converter circuits. More particularly, the present invention relates to an analog-to-digital converter circuit and method having a programmable resolution.
2. Background Information
A conventional Flash analog-to-digital converter (ADC) is a circuit which converts an analog input signal to a digital output signal at high speed. Flash ADCs are well suited to applications requiring large bandwidth. The number of bits at the output of these circuits varies, with those circuits having the greater number of output bits having the greater resolution and a greater potential accuracy. A disadvantage of flash ADCs is that the circuitry for high resolution output flash converters grows exponentially as the number of bits of resolution increases. A further disadvantage of flash ADCs is that they consume large amounts of power and area, and, thus, can be quite expensive. Hence, flash ADCs are generally reserved for high frequency applications that cannot be addressed using other slower ADCs. Flash ADC applications include, for example, satellite communication, radar processing, sampling oscilloscopes, high-density disk drives, and the like.
A conventional flash ADC circuit 100 is illustrated in FIG. 1. The ADC circuit 100 achieves an n-bit conversion by using a resistor network of 2n resistors and 2n comparators. The conventional flash ADC circuit 100 comprises a resistive network of 2n resistors including a first resistor 112, a second resistor 114, and up to a 2nth resistor 116. The voltage node between each resistor in the resistive network provides a reference voltage up to the topmost node (Vref) 101. An input signal (Vin) 103 is provided to a comparator network of 2n comparators including a first comparator 122, a second comparator 124, and up to a 2nth comparator 126. The comparators compare a given voltage from the resistive network to the input signal (Vin) 103. The output of the comparators is provided to a logic circuit 132, where the output is decoded to the appropriate digital output signal (adcout) 105.
Another conventional flash ADC, also called as a two-step flash ADC, is illustrated in FIG. 2. The two-step conventional flash ADC 200 achieves an n-bit conversion by employing a resistor network of 2n resistors and a comparator network of 2n-2 comparators. The two-step conventional flash ADC 200 comprises a resistive network of 2n resistors including a first resistor 212, a second resistor 214, and up to a 2nth resistor 216. Similar to the conventional flash ADC 100, the resistor network in the two-step flash ADC 200 provides several reference voltages up to the topmost resistor node voltage (Vref) 201. An input signal (Vin) 203 is provided to a comparator network of 2n-2 comparators including a first comparator 222, a second comparator 224, and up to a 2n-2th comparator 226. The output of the resistor network is provided to a switching network 210. The conventional two-step Flash ADC 200 performs two conversions, a coarse conversion and a fine-tuned conversion, of the input signal 203. The switching network 210 is reconfigured by the output of the coarse conversion. The circuitry for the switching network 210 varies by implementation choice. For example, such circuitry can comprise a Digital-to-Analog converter (DAC), a subtraction circuit, another lesser-resolution Flash ADC, or the like. The circuitry in the switching network 210 is generally set on clock phases to determine whether a coarse or fine conversion is being performed. The output of the switching network 210 is further provided to the comparators. The output of the comparators is provided to a logic circuit 220, where the output is decoded to generate an appropriate digital output signal (adcout) 205.
A disadvantage of the conventional flash ADC 100 is that as the conversion resolution increases, there is an exponential growth of the die area and an increase in die cost as the number of bits of resolution ‘n’ increases, due to the array of 2n resistors and 2n comparators required.
A disadvantage of the conventional flash ADC 200 is that although the numbers of comparators has been reduced, a complicated switching network and additional circuitry are still required, which consumes area and power.
A disadvantage of conventional two step ADCs is that they are not programmable to only use the coarse step when less accuracy and higher conversion speed are required. Conventional two-step analog to digital conversion methods require a resistor element of very high accuracy, which increases the design complexity of the Analog to Digital converter.
It would be desirable to provide an improved ADC having a higher resolution, programmability, and a faster conversion speed with a minimal increase in die area and power consumption.